The present disclosure relates to a semiconductor device, and is suitably used in a semiconductor device including a level shifter for converting a lower-potential side voltage level of an input signal to a negative high voltage, for example.
A nonvolatile memory circuit including a logic circuit mixed thereinto uses a low-voltage power supply (VDD, for example, about 1.0 V), a medium voltage power supply (VCC, for example, about 3 V), a positive high-voltage power supply (VPP, for example, about 11 V at most), and a negative high-voltage power supply (VEE, for example, about −8 V at most), for example.
Specifically, a low power-supply voltage VDD is used in a logic circuit portion. A medium power-supply voltage VCC is used in a peripheral circuit in a nonvolatile memory. A positive high voltage VPP is used for wiring data to a nonvolatile memory cell. A negative high voltage VEE is used for erasing data from a nonvolatile memory cell. The positive high voltage VPP is generated by boosting the medium power-supply voltage VCC. The negative high voltage VEE is generated by boosting a reference voltage VSS (0 V) to a negative direction.
In a peripheral circuit of a nonvolatile memory, level shifters are provided. One converts a VDD/VSS-level signal (that is, a signal of which a high level is the low power-supply voltage VDD and a low level is the reference voltage VSS) into a VPP/VSS-level signal. The other converts a VDD/VSS-level signal into a VDD/VEE-level signal. Hereinafter, the former level shifter that uses the positive high voltage VPP is referred to as a positive-voltage level shifter, and the latter level shifter that uses the negative high voltage VEE is referred to as a negative-voltage level shifter.
The negative-voltage level shifter has to operate even when the negative high-voltage power supply is inactive, that is, the reference voltage VSS is supplied in place of the negative high voltage VEE. As such a negative-voltage level shifter that can operate both when the negative power supply is active and when the negative power supply is inactive, there is known a negative-voltage level shifter disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-308092.
Specifically, the negative-voltage level shifter described in this document includes a pair of cross-coupled NMOS (N-channel Metal Oxide Semiconductor) transistors coupled a line for supplying the negative power-supply voltage VEE and a pair of input PMOS (P-channel MOS) transistors coupled to a line for supplying the power-supply voltage VDD, and a breakdown-voltage relaxing circuit. The breakdown-voltage relaxing circuit includes a pair of PMOS transistors and a pair of NMOS transistors for breakdown-voltage relaxation. To the gates of the breakdown-voltage relaxing NMOS transistors, the reference voltage VSS is supplied when the negative power supply is active, and the power-supply voltage VDD is supplied when the negative power supply is inactive.